1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage system, and particularly, to a non-volatile semiconductor storage system enabled to store two bit or more data in one memory cell.
2. Description of the Related Art
One of the well-known non-volatile semiconductor storage devices is a NAND cell type flash memory. The NAND cell type flash memory includes a memory cell array including a plurality of NAND cell units. Each NAND cell unit includes a plurality of memory cells connected in series and two selection transistors connected to both ends thereof. The memory cell holds, in an erase state, data “1” having a negative threshold voltage. In a data write operation, a floating gate is injected with electrons to rewrite data “0” having a positive threshold voltage. The NAND cell type flash memory may change the threshold voltage only from a lower value to a higher value in a data write operation, and may change the threshold voltage in the reverse direction (from a higher value to a lower value) only by an erase operation per a block.
For the purpose of increasing the memory capacity, a so-called multi-value NAND cell type flash memory has recently been developed, which stores two bit or more data in one memory cell. By way of example, a four-value NAND cell type EEPROM may store four-value (two-bit) data (“00,” “01,” “10,” and “11”) in a memory cell.
An n-value NAND cell type EEPROM includes a plurality of latch circuits per a single bit-line connected to the selected memory cell (see, for example, JP 2004-192789 (paragraphs from 0025 to 0139 and others). Specifically, when n-value data is written or read to or from the selected memory cell, the latch circuits serve to temporarily store the n-value data. For a four-value NAND cell type EEPROM, for example, in a write or a read operation, four-value (two-bit) data is temporarily stored in two latch circuits provided per one bit-line connected to the selected memory cell.
Such a multi-value storage scheme, however, has increased a probability of fail bit occurrence in a memory cell array greatly as the memory cell is miniaturized, thus lowering the yield of non-volatile memory chips. In considering this situation, a memory with an error correction circuit using an error correction code (ECC) in order to guarantee data reliability of a memory cell has been proposed (for example, see JP 2002-251884 (Paragraph 0026-0030 etc.))
However, in an n-value storage flash memory, it is necessary to set up n types of threshold voltage distributions. This causes the distances between the threshold voltage distributions or data margins to be smaller than those in a two-value (binary) storage flash memory. As “n” becomes larger, the data margin becomes smaller (in some cases, some distributions overlap one another, thus making the margin disappear), and it is likely that the probability of write error becomes larger. If the probability of write error becomes higher, conventional ECC circuit cannot deal with this problem.